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Why do Ethernet standards mostly come in 10x orders of magnitude, anyway?

10 -> 100 -> 1000 -> 10G -> 100G

I know there are some oddball 25G, 40G, and 2.5G out there too, but always wondered this.



Think about it this way: what's the minimum improvement you'll pay a whole heap of money for?

Each generation gets introduced with new switches, new NICs, and new cabling. Since 100Mb it has been possible to have link aggregation groups, where two or more cables on the same number of NICs on each side are bundled together into one bandwidth device. At some point you need to decide that it's worth doing the transition -- and 10x is a pretty good number for that.

The recent oddballs are 50G, 40G, 25G and 2.5G. All of them come from the idea of taking a higher speed NIC and adding a little more hardware to get multiple PHY transceivers -- a 100G becomes 2x50 or 4x25, and a 10G becomes 4x2.5.

Oddly, 40G comes from 4x10G in the other direction, and is more expensive to produce than 50G equipment. It's not very popular.


40G is quite common, and probably the most cost effective high speed open on the ebay-old-enterprise-gear market or at least was for a long time until maybe just now.

I started to write that there are $30 single-fiber-pair CWDM pluggables for 40GB making it the fastest speed you can do cheaply at distances longer than realistic for DAC cables... but checking ebay I see that there are now 100G pluggables for $39, so maybe its time to update the last of my 40G hosts to 100G.


Only 2.5G is an oddball. (I guess consumers are scared of fiber or too lazy to pull it)

40G QSFP is just 4 lanes of 10G and can usually be broken out into separate ports

Same for 100G QSFP28 (4 lanes of 25G SFP28)

You see this all the time with interfaces. Like with PICe bifurcation. Or how 56G infiniband is 4 lanes of 14G tho you can’t split it, etc


Physical. Look at what is behind the PHY.

https://en.m.wikipedia.org/wiki/SerDes https://en.m.wikipedia.org/wiki/XAUI

First 10G was 4x3.25G SerDes, so 4 traces to route on the board to the switch chip. There is some overhead in the signaling so you get 10G. If you plugged in a 1G, it just used one lane. Move to 40G, each lanes speed went up, 12G IIRC. At this point there was room for MAC/PHY so you go break each out to 4x10G. 256 traces to route to switch ASIC. Board routing is black magic. PHYless (no separate physical PHY chip required each set of 4 traces to be the same length down to the nm). Arista 7050 was first switch that shipped this. First 100G was 10 lanes, but lots of traces so smaller number of ports. Then they got the lanes up to 28G so you got 100G port for 4 lanes again, or 4x25G. So paired with MAC/PHY you could get 4x25G, 2x50, etc. and so on and so on as the speeds on the SerDes goes up. This is a simplified write up but mostly correct.


https://en.wikipedia.org/wiki/IEEE_802.3

I suspect it's about us having 10 fingers and using arabic numerals.




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